74LS147 Decimal to BCD Priority Encoder IC – DIP-16 Package

74LS147 Decimal to BCD Priority Encoder IC – DIP-16 Package

The SN54/74LS147 and the SN54/74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest-order data line is encoded. Both devices have data inputs and outputs which are active at the low logic level. The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a high logic level. The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By
providing cascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allowed without needing external circuitry. The SN54/74LS748 is a proprietary Motorola part incorporating a built-in glitches network that minimizes glitches on the GS output. The glitch occurs on the negative-going transition of the EI input when data inputs 0–7 are at logical ones. The only dc parameter differences between the LS148 and the LS748 are that (1) Pin 10 (input 0) has a fan-in of 2 on the LS748 versus a fan-in of 1 on the LS148; (2) Pins 1, 2, 3, 4, 11, 12 and 13 (inputs 1, 2, 3, 4, 5, 6, 7) have a fan-in of 3 on the LS748 versus a fan-in of 2 on the LS148. The only ac difference is that tPHL from EI to EO is changed from 40 to 45 ns.

Features/Specs:

• Series: 74LS147
• Function: Decimal to BCD Priority Encoder
• Technology Family: LS
• Supply voltage: 4.75V to 5.5V
• The frequency at nominal voltage: 35 MHz
• Typical propagation delay: 21nS
• Low power consumption: 32mW
• Operating temperature: 0ºC to 70ºC
• ESD CDM (kV): 0.75
• ESD HBM (kV): 2
• Balanced propagation delays
• Designed specifically for high speed
• IOL Current Max: 8mA
• IOH Current Max: -0.4mA
• Number of Bits: 4
• Number of Channels: 2
• Configuration: 2:4 & 8:3
• Mounting Style: Through Hole
• Package/Case: DIP-16

Package includes:

• 1 x 74LS147 Decimal to BCD Priority Encoder IC – DIP-16 Package