CD4015 IC Dual Shift Register
The MC14015B dual 4–bit static shift register is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. It consists of two identical, independent 4–state serial–input/parallel–output registers. Each register has independent Clock and Reset inputs with a single serial Data input. The register states are type D master-slave flip–flops. Data is shifted from one stage to the next during the positive-going clock transition. Each register can be cleared when a high level is applied on the Reset line. These complementary MOS shift registers find primary use in buffer storage and serial–to–parallel conversion where low power dissipation and/or noise immunity is desired.
- Wide supply voltage range 3.0V to 18V
- High noise immunity 0.45 VDD (typ.)
- Diode Protection on All Inputs
- Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS
- Medium speed operation 8 MHz (typ.) clock rate Y Fully static design @VDD b VSS e 10V
Datasheet: CD4015 IC Dual Shift Register
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